1. Field of the invention
This invention relates to an improved logic circuit for switching noise reduction, which is suitable for an integrated circuit logical data input or output circuit having a plurality of input terminals or output terminals whose logic status changes at fast speed, independently of each other.
2. Brief description of the related art
In the field of logic circuitry, especially input or output operations in an integrated circuit, such as a microprocessor, there has been a need for a faster and error free data input or data output circuit.
However, faster input/output operations in the data input or data output circuits generally cause more data errors. The cause of such data errors may be explained in the following examples.
FIG. 1 illustrates a general block diagram of an example of a conventional output buffer circuit 2 utilized in a microprocessor (not shown). In this example, a plurality of three-state output buffer circuits 8-1, 8-2, . . . 8-n (n:integer, n&gt;2) are provided between a common voltage source line 4 which is connected to a voltage source Vcc (+5 V) and a common ground line 6 which is connected to a ground level Vss.(0 V)
Each of the three-state output buffer circuits 8-1, 8-2, . . . 8-n receives one corresponding input data signal IN-1, IN-2, . . . IN-n respectively, which has either a "H" (+5 V) level or "L" (0 V) level. Further, the three-state output buffer circuits 8-1 to 8-n output the input data signals to output terminals 10-1, 10-2 . . . 10-n thereof respectively in response to each of corresponding "H" level data control signals CS-1, CS-2, . . . CS-n.
On the other hand, in case that the data control signals CS-1, CS-2, . . . CS-n have a "L" (0 V) level, the three-state output buffer circuits 8-1, 8-2, . . . 8-n enter a high impedance state.
Because the three-state output buffer circuits 8-1, 8-2, . . . 8-n operate independently of each other, switching noise is generated in the following condition.
Assume that all of the data control signals CS-1 to CS-n at a "H" level,(2) (1) all of the input data signals IN-1 to IN-n except IN-n become "L" level from the previous at a "H" level, (3) and only the input data signal IN-n maintains its "L" level in the same timing.
In this condition, the three-state output buffer circuits 8-1, 8-2, . . . 8-n except one output buffer circuit 8-n outputted "H" level signals and positive electric charges were charged in the output terminals 10-1, 10-2, . . . 10-(n-1). If the three-state output buffer circuits 8-1, 8-2, . . . 8-(n-1) output "L" level signal simultaneously, all of those positive electric charges flow into the common ground line 6 and generate an inductive switching noise on the common ground line 6. The switching noise further generates a derived switching noise on the output terminal 10-n which must maintain its, "L" level status.
FIG. 2 illustrates the signal conditions of the output terminals 10-1, 10-2, . . . 10-n under above mentioned situation. In FIG. 2, a signal status A illustrates signal status of the output terminals 10-1, 10-2, . . . 10-(n-1) and a signal status B illustrates signal status of the output terminal 10-n. At the output terminal 10-n, a switching noise NZ-1 appears at the falling edge of the signal status A shown as waveform B in FIG. 2. Such switching noise NZ-1 can cause data error of the output buffer circuit 2.
Further, similar phenomenon could be appear in case of a data input circuit if the data input circuit has a similar circuit structure to that of the output buffer circuit 2. For example, if the data input circuit comprises a plurality of input buffer circuits which are provided between a common voltage source line and a common ground line, operating independently of each other, such switching noise could appear on an input terminal of one of the data input circuits under the above mentioned condition.
To avoid such problems, there were some known modifications. One of the simplest ways to eliminate such switching noise is to prepare respective ground lines for respective output or input circuits to conduct the switching noise away. However, for an integrated circuit on a silicon substrate which must conserve space, it is wasteful and impractical to prepare such ground lines for each of the buffer circuits.
The other usual way to suppress such switching noise is to include a capacitance load for absorbing the switching noise at the output terminals. However, if possible, such loads should be eliminated for saving cost and space in an integrated circuit. Therefore, attention is given to the as to circuit structure itself for switching noise reduction.
FIG. 3 and FIG. 4 are drawings for explaining an example of such modifications utilized in an output buffer circuit for a microprocessor. Assume that an output buffer circuit 12 illustrated in FIG. 3 is one of the three-state output buffer circuits 8-1 to 8-n illustrated in FIG. 1. The output buffer circuit 12 is provided between a common voltage source line 14 which is connected to a voltage source Vcc (+5 V) and a common ground line 16 which is connected to a ground level Vss (0 V).
The output buffer circuit 12 includes a NAND gate 24 which receives an input signal IN-x (x:integer, 0&lt;x.ltoreq.n) via an input signal line 20 and a control signal CS-x via a control signal line 22, a NOR gate 30 which receives the input signal IN-x and an inverted control signal CS-x via an inverter 28. An output of the NAND gate 24 is applied to a gate terminal of a P-channel type MOS (hereinafter, PMOS) transistor 26 whose drain terminal is connected to the common voltage source line 14 and whose source terminal is connected to an output terminal 18 of the output buffer circuit 12.
Further, there are provided five n-channel type MOS (hereinafter, NMOS) transistors 32-1, 32-2, 32-3, 32-4, and 32-5 in parallel between the common ground line 16 and the source terminal of the PMOS transistor 26. In detail, all of the drain terminals of the NMOS transistors from 32-1 to 32-5 are connected to the source terminal of the PMOS transistor 26, and all of the source terminals of the NMOS transistors from 32-1 to 32-5 are connected to the common ground line 16.
Further, an output of the NOR gate 30 is applied to a gate terminal of the first NMOS transistor 32-1 and also applied to the other gate terminals of the other (second to forth) NMOS transistors from 32-2 to 32-5 gradually delayed by four delay circuits 34-1, 34-2, 34-3, and 34-4. The delay circuit itself is a conventional circuit and it could be possible to provide such delay circuit by means of a plurality of (as an even number) of serially connected inverter circuits or a conventional time constant circuit.
As a result, the output buffer circuit 12 outputs a logic status of an inputted signal IN-x on the input signal line 20 to an output terminal 18 in response to a "H" level control signal CS-x applied via the control signal line 22. If the control signal CS-x is "L" level, the output buffer circuit 12 becomes high impedance status.
Further, since a switching timing provided by the NOR gate 30 is delayed respectively by the delay circuits 34-1 to 34-4, any switching noise is also delayed gradually and suppressed enough to avoid a data error.
FIG. 4 is a drawing for explaining an effect of the modification provided in the output buffer circuit 12 illustrated in FIG. 3 and illustrates a similar situation to that of FIG. 2.
For example, even if the other output buffer circuits (not shown) change their output signal from "H" level to "L" level and only the output buffer circuit 12 maintain its "L" level, the positive electric charges flow into the common ground line 16 and will be diffused by the delay circuits. As a result, the inductive noise will be suppressed.
In FIG. 4, status C is a signal status of the output terminals of the other output buffer circuits (not shown) and status D is a signal status of the common ground line 16. As shown in FIG. 4, a switching noise NZ-2 is diffused during a switching timing T. As a result, its wave height is suppressed enough to avoid a data error.
However, the above mentioned modification has the disadvantage of needing a plurality of NMOS transistors and delay circuits for each of output buffer circuits. For an integrated circuit which must conserve space, it is a serious disadvantage. Further, because there are a plurality of NMOS transistors and delay circuits to be coupled, the switching time T of the output buffer circuit 12 itself becomes extremely long. Therefore, the modification could not be applied to a high speed output buffer circuit. Further, even the wave height is low, there still remains a switching noise (FIG. 4, curve D).